1. Technical Field
The present invention relates to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits, in particular, integrated circuits that use MOS transistors, continue to achieve ever higher integration density. Due to increasing integration density, MOS transistors used therein have been miniaturized to a nanometer scale. Increasing miniaturization of MOS transistors renders it difficult to suppress leak current and a problem has arisen in which the area occupied by the circuit cannot be decreased while obtaining a required amount of current. In order to address this problem, a surrounding gate transistor (hereinafter referred to as an SGT) has been proposed, in which a source, a gate, and a drain are arranged in a direction perpendicular to the substrate and a gate electrode surrounds a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
According to a typical SGT production method, a silicon pillar having a pillar-shaped nitride film hard mask is formed by using a mask for lithographically forming a silicon pillar, a planar silicon layer is formed at a bottom of the silicon pillar by using a mask for lithographically forming a planar silicon layer, and a gate line is formed by using a mask for lithographically forming a gate line (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317).
In other words, three masks are used to form a silicon pillar, a planar silicon layer, and a gate line.
A metal-gate-last process in which a metal gate is formed after a high-temperature process has been employed in actual production of typical MOS transistors in order to integrate a metal gate process and a high-temperature process (refer to IEDM 2007, K. Mistry et. al, pp 247-250). A gate is formed by using polysilicon, an interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and etched, and then a metal is deposited. Thus, a metal-gate-last process in which a metal gate is formed after a high-temperature process must be employed in making SGTs in order to integrate a metal gate process and a high-temperature process.
In order to decrease a parasitic capacitance between a gate line and a substrate, a first insulating film is used in a typical MOS transistor. For example, in a FINFET (refer to IEDM 2010, C C. Wu, et. al, 27.1.1-27.1.4), a first insulating film is formed around one fin-shaped semiconductor layer, and etched back to expose the fin-shaped semiconductor layer and decrease the parasitic capacitance between the gate line and the substrate. Thus, in SGTs also, a first insulating film must be used in order to decrease the parasitic capacitance between the gate line and the substrate. Since an SGT includes a pillar-shaped semiconductor layer in addition to a fin-shaped semiconductor layer, some consideration is necessary to form a pillar-shaped semiconductor layer.